Large numbers of DRAM cells must be interconnected with wordlines, and wordlines and spaces between wordlines are a factor in determining the size of a folded-bitline cell. Typically, wordlines are formed as thin films of a conductor, such as aluminum or polysilicon, deposited on insulating materials on the semiconductor surface and defined as lines photolithographically. Efforts to shrink wordlines and the spaces between wordlines are limited since both line widths and spaces cannot photolithographically be made smaller than the line width, for example, decreasing the line width usually increases the line-to-line spacing and so the overall wordline pitch is not improved. The cost of decreasing the photolithographic minimum dimension is high, and each such effort has defined succeeding generations of semiconductor products. In each generation of DRAM cells, the photolithographically defined wordline and/or it's associated space have thus been formed at the photolithographic minimum dimension. Each such effort has defined succeeding generations of semiconductor products. In each generation of DRAM cells, the photolithographically defined wordline and/or its associated space have thus been formed at the photolithographic minimum dimension.
In the folded-bitline DRAM cell design, both an active and a passing wordline pass through each cell, as illustrated in commonly assigned U.S. Pat. No. 4,801,988 ("the '988 patent"), issued to D. M. Kenney, entitled "Semiconductor Trench Capacitor Cell with Merged Isolation and Node Trench Construction," and shown therein which is incorporated herein by reference. Crossing over trench capacitors 505A and 510A for a pair of cells in FIG. 1, are wordlines 515A and 520A. The space required for such a DRAM cell is a minimum dimension for each of the two wordlines in each cell and an additional minimum dimension for each space between each wordline. Thus the total minimum length of the traditional folded bitline cell is 4 minimum dimensions. The width of the cell is at least two minimum dimensions, of which one is for the components in the cell and the other is for a thick isolation (a trench capacitor can be a part of this isolation) in the space between cells. Thus, the minimum area of a traditional cell has been 8 square minimum dimensions, or 8 squares.
One approach to avoid the photolithographic limit is to provide a wordline formed of a conductive sidewall rail. The width of such rails is determined by the thickness of the deposited conductor, and this thickness can be significantly less than a minimum photolithographic dimension. Commonly assigned U.S. Pat. No. 5,202,272 ("the '272 patent"), issued to Hsieh, entitled "Field Effect Transistor Formed With Deep-Submicron Gate," and U.S. Pat. No. 5,013,680 ("the '680 patent"), issued to Lowrey, entitled "Process for Fabricating a DRAM Array Having Feature Widths that Transcend the Resolution Limit of Available Photolithography," all of which are incorporated herein by reference, teach methods of using a subminimum dimension conductive sidewall spacer rail to form a wordline.
One problem encountered in the use of such subminimum dimension spacer rail wordlines is the difficulty of precisely controlling the length of the device and the extent of lateral diffusion of the source and drain. For example, small variations of spacer thickness or lateral diffusion can result in a large variation in the length of the subminimum dimension channel. The result can be large leakage currents on the one hand and degraded performance on the other. The present invention avoids the difficulties of the subminimum dimension sidewall spacer rail wordlines of the prior art.
Moreover, many prior art structures and techniques for sublithographic wordlines and/or bitlines do not provide a bitline contact which is borderless to the wordline.